The design and fabrication of three-dimensional memory arrays present significant engineering challenges. For example, architectures for three-dimensional resistance-switching random access memory (RRAM) may require numerous photolithographic processing steps to fabricate the memory array, resulting in a complicated manufacturing process with a high cost per bit. High parasitic wiring resistance also presents challenges in traditional architectures for three-dimensional RRAMs. Accordingly, there is a need for improved three-dimensional memory (e.g., RRAM) architectures.
Like reference numerals refer to corresponding parts throughout the drawings.